1. Technical Field
This disclosure relates to semiconductor devices, and more particularly, to a semiconductor memory device with bitline equalization in twisted bitline regions.
2. Description of the Related Art
Many current dynamic random access memory (DRAM) devices employ bitlines (BL) for reading and writing data to storage capacitors of memory cells. Many DRAM designs employ a bitline for each 512 memory cells (e.g., 512 bits/BL). To reduce bitline to bitline coupling effects, a bitline twist is introduced. These twists consume layout space.
Referring to FIG. 1, a schematic diagram of semiconductor memory bitline architecture is illustratively shown. The bitline architecture shows a memory array 10 having a plurality of bitlines 12. Bitlines 12 are paired. Each pair of bitlines includes a bitline true (BLt) and a bitline complement (BLc). Each pair is indexed in FIG. 1 to designate the pair, e.g., BLc.sub.i and BLt.sub.i, where i =1, 2, 3, . . . for pair number 1, pair number 2, etc. Each pair is coupled to a sense amplifier (SA) 14. Every other BL pair includes a twist 16. Twists 16 are employed to reduce bitline coupling between adjacent bitlines, i.e., a portion of BLt's and BLc's are separated from adjacent or nearby BLt's and BLc's to prevent cross-talk when the adjacent or nearby BLt's and BLc's are simultaneously activated. In one example, the layout area consumed by twists 16 includes a width of 6 times the pitch of a wordline 18. Wordlines 18 in a region 20 are dummy wordlines, which are inactive as a consequence of twists 16 in this region. The twist region 20 has no active functionality, it merely serves to cross true and complement BL's every other BL-pair.
Because sense amplifiers 14 sense charge differences between BL's, the BL's need to be equalized after each active cycle. Equalizing transistors 22 are connected across each pair of BL's (e.g., BLc.sub.1 and BLt.sub.1). Transistors 22 are activated by an equalize signal (EQU) to permit conduction between each pair of BL's before the next active cycle of the BL's. Transistors 22 are located near sense amplifiers 14 on one end of each pair of BL's 12. The time needed to equalize the BL's, especially for long bitlines (e.g., 512 bits/BL architectures), before the next activate (ACT) command can be issued limits chip performance.
Referring to FIG. 2, an illustrative timing diagram is shown for employing BL's. The following signals are represented: a global clock signal (CLK), a row address strobe (RAS), a column address strobe (CAS) a write enable (WE), an address line (ADR) and an output line signal (DQ). The following command are also shown: activate (ACT), precharge (PRE), write (WRT) and read (READ). tRP (or row address strobe (RAS) to Precharge) represents the time it takes to equalize BL's before the ACT command.
Therefore, a need exists for reducing the time needed to equalize bitlines without chip layout penalty. A further need exists for a layout, which employs the inactive region caused by bitline twists.